2008-02-27

UltraSPARC T1 vs. T2

Some time ago I had to briefly compare the UltraSPARC T1 (aka Niagara) vs. the T2. I'm going to loose the sheet with my notes, so before it finally happens I will report that table here:


UltraSPARC T1

UltraSPARC T2

Technology

TI 90nm, 9LM

TI 65nm

Max Frequency

1200 MHz

1400 MHz

Transistors

279M


Total die area

378 mm2

342 mm2

CPU core area

11 mm2

12 mm2

Total pins

1933 BGA

1831 BGA

Power Dissipation

70W

95W typical (60 to 123)

Cores per die

8

8

Threads per core

4

8

Total threads

32

64

ISA

SPARC v9 + VIS subset

SPARC v9 + full VIS 2.0

Pipeline stages

6 int

8 int, 12 fp

Integer ALUs

8

16

FPUs

1

8

Load/Store Units

8

8

Crypto Units

8 small

8 large

Max IPC

8

16

Max MIPS

9'600

22'400

L1-I$

16KB, 4-way, 32B line

16KB, 8-way, 32B line

L1-D$

8KB, 4-way, 16B line

8KB, 4-way, 16B line

I-TLB

64 entry, fully assoc.

64 entry, fully assoc.

D-TLB

64 entry, fully assoc

128 entry, fully assoc.

L2 Caches

4 banks x 3 MB, 12-way, 64B line

8 banks x 4 MB, 16-way, 64B line

Memory Controllers

4 x DDR2 @ 200 MHz

4 x FB-DIMM @ 667 MHz

Memory Bandwidth

25 GB/s

60 GB/s

Supported mem. size

128 GB

128 GB

Integrated I/O

Jbus (legacy)

PCI-Express x8

Integrated I/O Bandwidth

3.2 GB/s

2.5 GB/s

Networking

-

2 x 10/1Gb Ethernet